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Computer Principles and Design in Verilog HDL

Computer Principles and Design in Verilog HDL

von: Yamin Li

Wiley, 2015

ISBN: 9781118841129 , 550 Seiten

Format: ePUB

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Computer Principles and Design in Verilog HDL


 

List of Figures


1.1 Computer system organization
1.2 Simplified structure of RISC CPU
1.3 Simplified structure of pipelined CPU
1.4 On-chip dedicated instruction cache and data cache
1.5 Simplified structure of a multithreading CPU
1.6 Simplified structure of a multicore CPU
1.7 Memory hierarchy
1.8 TLB maps virtual address to physical address
1.9 I/O interfaces in a computer system
1.10 Amdahl's Law examples
1.11 Trace-driven simulation
1.12 Execution-driven simulation
1.13 Supercomputer and interconnection network
1.14 Waveform of time counter
2.1 Three basic gates and four common gates
2.2 Karnaugh map for a 2-to-1 multiplexer
2.3 Schematic diagram of a 2-to-1 multiplexer
2.4 Waveform of a 2-to-1 multiplexer
2.5 Schematic diagram of a CMOS inverter
2.6 Schematic diagram of NAND and NOR gates
2.7 Schematic diagram of AND and OR gates
2.8 Implementing a multiplexer using only NAND gates
2.9 Implementing a multiplexer using CMOS transistors
2.10 Schematic diagram of multiplexer using tri-state and ordinary gates
2.11 Schematic diagram of decoder with enable control
2.12 Decoder and encoder
2.13 Waveform of a 8-3 priority encoder
2.14 A 1-to-8 demultiplexer
2.15 Schematic diagram of 32-bit left shifter
2.16 Schematic diagram of 32-bit barrel shifter
2.17 Schematic diagram of a D latch
2.18 Waveform of a D latch
2.19 Schematic diagram of an academic D flip-flop
2.20 Waveform of an academic D flip-flop
2.21 Schematic diagram of an industry D flip-flop
2.22 Waveform of an industry D flip-flop
2.23 Schematic diagram of a D flip-flop with enable control
2.24 Schematic diagram of the JK latch
2.25 Schematic diagram of the JK flip-flop
2.26 Waveform of the JK flip-flop
2.27 Schematic diagram of the T latch
2.28 Schematic diagram of the T flip-flop
2.29 Waveform of the industry T flip-flop
2.30 Schematic diagram of a shift register
2.31 Schematic diagram of a FIFO of depth 4
2.32 Waveforms of FIFO 4
2.33 A circular FIFO implemented with RAM
2.34 Waveforms of RAM-based FIFO
2.35 Two models of the general finite state machine
2.36 A counter with a seven-segment LED
2.37 Block diagram of a counter with a seven-segment LED
2.38 State transition diagram of the counter
2.39 Karnaugh map for next state of the counter
2.40 Karnaugh map for the output function of the counter
2.41 Schematic diagram of 3-bit D flip-flops
2.42 Schematic diagram of next state for the counter
2.43 Schematic diagram of output function for the counter
2.44 Schematic diagram of the counter with a seven-segment LED
2.45 Waveform of the up/down counter
3.1 Bit's significances of a 16-bit unsigned binary number
3.2 Bit's significances of a 16-bit 2's complement signed number
3.3 Addition of two 4-bit numbers
3.4 Schematic diagram of the full adder
3.5 Schematic diagram of full adder (using XOR gates)
3.6 Waveform of the full adder
3.7 Schematic diagram of 4-bit ripple adder
3.8 Schematic diagram of a 4-bit adder/subtracter
3.9 Waveform of a 4-bit adder/subtracter
3.10 Four-bit carry-lookahead adder
3.11 Waveform of the carry-lookahead adder
3.12 Multiplication of two 8-bit signed numbers
3.13 Implementing a signed multiplier using NAND gates
3.14 Waveform of a signed multiplier
3.15 First level of the 8-bit Wallace tree
3.16 Adders for 7th bit in the 8-bit Wallace tree
3.17 Schematic diagram of the 8-bit Wallace tree
3.18 Waveform of the 8 × 8 Wallace tree (partial product)
3.19 Waveform of 8 × 8 Wallace tree (product)
3.20 Schematic diagram of a restoring divider
3.21 Waveform of a restoring divider
3.22 Schematic diagram of a nonrestoring divider
3.23 Waveform of a nonrestoring divider
3.24 Schematic diagram of the Goldschmidt divider
3.25 Waveform of the Goldschmidt divider
3.26 Schematic diagram of 32-bit Newton–Raphson divider
3.27 Waveform of the Newton–Raphson divider
3.28 Schematic diagram of restoring square rooter
3.29 Waveform of the restoring square rooter
3.30 Schematic diagram of a nonrestoring square rooter
3.31 Waveform of a nonrestoring square rooter
3.32 Schematic diagram of the Goldschmidt square rooter
3.33 Waveform of the Goldschmidt square rooter
3.34 Schematic diagram of the Newton–Raphson square rooter
3.35 Waveform of the Newton–Raphson square rooter
4.1 ISA as an interface between software and hardware
4.2 Little endian and big endian
4.3 Data alignment in memory locations
4.4 Instruction architecture
4.5 MIPS instruction formats
4.6 Stack for function call
4.7 Pointer of a variable
4.8 AsmSim main window
4.9 AsmSim program editor window
4.10 AsmSim graphics console...