Hardware Acceleration of EDA Algorithms - Custom ICs, FPGAs and GPUs

This book deals with the acceleration of EDA algorithms using hardware platforms such as FPGAs and GPUs. Widely applied CAD algorithms are evaluated and compared for potential acceleration on FPGAs and GPUs. Coverage includes discussion of conditions under which it is preferable to use one platform over another, e.g., when an EDA problem has a high degree of data parallelism, the GPU is typically the preferred platform, whereas when the problem has more control, an FPGA may be preferred. Results are presented for the acceleration of several CAD algorithms (fault simulation, fault table generation, model card evaluation in SPICE, Monte Carlo statistical static timing analysis), demonstrating speedups from 30X to 800X. This book serves as a valuable guide on how best to leverage parallelism to accelerate CAD algorithms. It also presents a methodology to extract automatically SIMD parallelism from regular uniprocessor code. With this approach, uniprocessor code can automatically be converted to GPU code, allowing for significant acceleration. This approach is particularly useful, since different GPUs have vastly different specifications, making the manual generation of GPU code an unscalable proposition. TOC:Introduction. Alternative Hardware Platforms. Hardware Platforms. GPU Architecture and CUDA Programming Model. Control Dominated Category. Accelerating Boolean Satisfiability on a Custom IC. Accelerating Boolean Satisfiability on an FPGA. Accelerating Boolean Satisfiability on a Graphics Processing Unit. Control Plus Data Parallel Applications. Accelerating Statistical Static Timing Analysis Using Graphics Processors. Accelerating Fault Simulation Using Graphics Processors. Fault Table Generation Using Graphics Processors. Accelerating Circuit Simulation Using Graphics Processors. Automated Approach for Graphics Processor Based Software Acceleration. Conclusions.