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Design of System on a Chip
von: Ricardo Reis, Jochen Jess (Eds.)
Springer-Verlag, 2004
ISBN: 9781402079290, 257 Seiten
Format: PDF, OL
Preis: 103,95 EUR
Ersparnis: 13,75 EUR
Contents
5
Design of Systems on a Chip: Introduction
7
1. MOORE™S LAW AND THE CONSEQUENCES
7
2. THE “INTERNATIONAL ROADMAP FOR SEMICONDUCTOR TECHNOLOGY&rdquo
11
3. THE “TECHNOLOGY SHOCKWAVE&rdquo
13
4. THE TYDE OF THE MARKETS
14
5. THE FIRST BOOK: SEMICONDUCTOR DEVICES AND COMPONENTS
17
6. REFERENCES
18
BJT Modeling with VBIC
19
1. INTRODUCTION
19
2. VBIC EQUIVALENT NETWORK
20
3. VBIC MODEL FORMULATION
22
4. PARAMETER EXTRACTION
34
5. RELATIONSHIP BETWEEN SGP AND VBIC PARAMETERS
36
6. VBIC DC MODELING
37
7. ELECTROTHERMAL EXAMPLES
39
8. HIGH FREQUENCY MODELING
40
9. CONCLUSIONS
45
10. ACKNOWLEDGMENTS
46
11. REFERENCES
46
12. BIOGRAPHY
47
A MOS Transistor Model for Mixed Analog-digital Circuit Design and Simulation
48
1. INTRODUCTION
49
2. THE LONG-CHANNEL MODEL
51
2.1 Transconductance-to-current ratio g
51
2.2 The static model for the drain current
57
2.3 Hand calculation model and circuit design
58
2.4 Vertical field dependent mobility
59
3. THE STATIC MODEL FOR SHORT AND NARROW GEOMETRIES
63
3.1 Velocity saturation and channel length modulation ( CLM)
65
3.2 Charge-sharing and reverse short-channel effect ( RSCE)
66
3.3 Drain induced barrier lowering (DIBL)
69
3.4 Gate voltage dependent series resistance
71
4. THE CHARGE AND THERMAL NOISE MODELS
73
4.1 Charges integration
73
4.2 Transcapacitances model
75
4.3 Noise model
77
5. MODEL APPLICATION AND EXPERIMENTAL RESULTS
78
5.1 The computer simulation model
78
5.2 Hierarchical model structure
79
5.3 Statistical circuit simulation including matching
79
5.4 The pinch-off voltage measurement and parameter extraction method
81
5.5 Parameter extraction sequence
85
5.6 Experimental results
87
6. CONCLUSIONS
91
7. ACKNOWLEDGMENTS
92
8. REFERENCES
92
Efficient Statistical Modeling for Circuit Simulation
95
1. INTRODUCTION
95
2. CLASSIFICATION OF STATISTICAL MODELS
97
3. HIERARCHY OF STATISTICAL VARIATIONS
98
4. PROCESS AND GEOMETRY LEVEL MODELING
99
5. EXISTING STATISTICAL MODELING APPROACHES
100
5.1 SPICE model parameter perturbation
100
5.2 Extreme case data
101
5.3 Forward propagation of variance
101
5.4 Numerical data fitting
103
6. TYPICAL CASE MODELING
104
7. DISTRIBUTIONAL STATISTICAL MODELING
105
8. SPECIFIC CASE STATISTICAL MODELING
108
9. GENERIC CASE STATISTICAL MODELING
110
10. SPECIFIC MOSFET EXAMPLE
111
11. CONCLUSIONS
119
12. REFERENCES
119
13. BIOGRAPHY
120
Retargetable Application-driven Analog-digital Block Design
121
1. INTRODUCTION
121
2. ANALOG-DIGITAL INTERFACE REQUIREMENTS
123
3. DESIGN FLOW AND CAD SUPPORT
125
3.1 Functional hierarchy
125
3.2 Top-down flow for electrical design
126
3.3 Bottom-up flow for layout
129
3.4 CAD limitations
129
4. RETARGETABLE BLOCK DESIGN
130
4.1 Retargetable block model
130
5. EXAMPLES FROM INDUSTRY PRACTICE
135
5.1 Quadrature D/A RF interface
135
5.2 Delta-sigma A/D interface
136
6. CONCLUSIONS
138
7. ACKNOWLEDGMENTS
138
8. REFERENCES
139
Robust Low Voltage Low Power Analog Mos VLSI Design
140
1. INTRODUCTION
141
2. LOW VOLTAGE CMOS SAQUARE-LAW COMPOSITE CELLS
141
3. STATISTICAL VLSI DESIGN TOOLS AND TECHNIQUES
145
3.1 Statistical Parameter Modeling
146
3.2 Parameter Variance Models for MOS Device Mismatch
146
3.3 Statistical Techniques
149
4. STATISTICAL DESIGN OF THE CMOS SQUARELAW CMOS CELLS
152
4.1 Example 1: Statistical Simulation of Cell1
152
5 ROBUST LOW VOLTAGE OPAMP DESIGN
159
5.1 Robust Low Voltage Rail-to-Rail Opamp Architecture
161
6. A SINGLE STAGE OPAMP DESIGN EXAMPLE
165
7. A TWO STAGE LOW VOLTAGE OPAMP DESIGN
169
8. STATISTICAL DESIGN AND OPTIMIZATION OF LOW VOLTAGE OPAMPS
171
8.1 DC Offset Simulation
173
8.2 Statistical Experiments
174
8.3 Optimization
178
8.4 Comparison and Discussion
180
9. CONCLUSION
181
10. ACKNOWLEDGMENTS
181
11. REFERENCES
181
12. BIOGRAPHY
182
Ultralow-Voltage Memory Circuits
185
1. INTRODUCTION
186
2. DESIGN ISSUES FOR ULTRALOW-VOLTAGE RAMS
187
2.1 Stable-Memory Cell Operation
187
2.2 Subthreshold Current Reduction
188
2.3 Suppression of or Compensation for Design- Parameter
192
2.4 Single Power-Supply and Power-Supply Standardization
193
3. DRAM CIRCUITS
194
3.1 Stable Memory - Cell Operation
196
3.2 Subthreshold Current Reduction
201
4. ULTRALOW-VOLTAGE SRAM CIRCUITS
217
5. PERSPECTIVES
219
5.1 SOI CMOS Technology
219
6 CONCLUSION
225
7. ACKNOWLEDGMENT
225
8. REFERENCES
226
Low-voltage Low-power High-speed I/O Buffers
228
1. INTRODUCTION
228
2. WHERE DOES THE POWER GO?
229
2.1 PAC
229
2.2 PDC
229
2.3 Poverlap
230
2.4 Pleakage
230
2.5 Pringing
230
3. VARIOUS TYPES OF BUFFERS
230
3.1 CMOS
231
3.2 HSTL (High-Speed Transistor Logic)
232
3.3 GTL/NTL (Gunning Transistor Logic / NMOS Transistor Logic)
232
3.4 PCML (Pseudo Current Mode Logic)
233
3.5 PECL (Pseudo Emitter Coupled Logic)
234
3.6 USB (Universal Serial Bus)
234
3.7 Matched-Impedance Buffer
235
3.8 Hyper-LVDS™ (Low-Voltage Differential Signals)
236
4. SUMMARY
237
5. CONCLUSION
237
6. REFERENCES
237
7. BIOGRAPHY
238
Microelectronics toward 2010
239
1. INTRODUCTION
239
2. TRENDS OF SEMICONDUCTOR TECHNOLOGY
240
3. PERSPECTIVES OF KEY TECHNOLOGIES
242
4. BREAKTHROUGHS FOR THE FUTURE DEVELOPMENT
251
4.1 Reduction of the number of transistors per function
251
4.2 Use of flexible circuits for high performance
253
5. CONCLUDING REMARKS
255
6. REFERENCES
256
7. BIOGRAPHY
256
Index of Authors
258
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